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High reliability triple redundant memory element with integrated testability and voting structures on each latch
High reliability triple redundant memory element with integrated testability and voting structures on each latch
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机译:高可靠性的三重冗余存储元件,每个锁存器具有集成的可测试性和表决结构
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摘要
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
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