Variable delay circuit and system LSI using the variable delay circuit

摘要

PPROBLEM TO BE SOLVED: To provide a system LSI of high-speed, small area and low power consumption by reducing the number of offsets, variable notch widths and transistors at a variable delay circuit. PSOLUTION: A multiplexer in the variable delay circuit is configured with a NMOS dynamic logic circuit. In order to give a duty ratio adjustment function to a delay generating circuit DGD composed of multiple stage invertors within the variable delay circuit 2, (two) input NAND gates 20 and 30 of which input is an input signal S and delay outputs G1 and G2 of previous stage, are provided. According to this arrangement, the duty ratio is simultaneously decreased in the process of delaying signals. PCOPYRIGHT: (C)2003,JPO