S-Band Variable Time Delay Circuit on Barium Tetratitanate.

摘要

The performance requirements for a variable time delay circuit for use in a phased array antenna are given - time delay from 1/2 to 16 nsec, 3 GHz operating frequency, 20% bandwidth, temperature compensation, and compact size. A brief description is presented of various types of devices which could meet these requirements. In the research for the electrical structure of this time delay circuit, two design types were investigated. The first, a tapped transmission line, yielded poor results on a test circuit - high insertion loss (2-22 db) and high VSWR. The second design was that of a 5-bit network. Test circuit results showed this to be a relatively good design - insertion loss of 0.7 - 5.0 db and VSWR of 1.8 and 2.5. A complete time delay circuit design was produced using a 4-bit structure for the RF transmission line (1/2 to 8 nsec in 1/2 nsec increments) and a loaded switched-line structure for selection of the amount of time delay. For temperature compensation, the circuit design was dimensioned for a barium tetratitinate microstrip substrate. Due to small substrate size, the maximum time delay was 8 nsec instead of 16 nsec.