PROBLEM TO BE SOLVED: To easily obtain a clock with high frequencies even at the time of low voltage driving by generating an output corresponding to a phase difference between the output of an arbitrary invertor serially connected in odd-numbered stages and the output of an invertor in the next stage, and generating the output of the logical sum of the outputs as a reference pulse output. SOLUTION: A voltage control oscillation circuit(VCO) 20 oscillators by serially connecting invertors 5-7 in odd-numbered stages, and feedbacking the output to an input, and sets oscillation frequencies according to a control signal from an outside part. Then, a control signal generating circuit constituted of a frequency-dividing circuit 13 and a phase comparator circuit 11 or the like generates a control signal by a PLL loop including the VCO 20. Then, NAND gates 26-28 of the VCO 20 receive the output of the arbitrary invertor in the odd-numbered stage and the output of the invertor in the next stage, and generates an output comesponding to a phase difference between those outputs. Moreover, an NOR gate 29 generates the output of the logical sum of the outputs of the NAND gates 26-28 as a reference pulse output from a clock output terminal 30.
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