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High voltage gain topology for analog circuits in short channel technologies
High voltage gain topology for analog circuits in short channel technologies
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机译:短通道技术中模拟电路的高电压增益拓扑
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摘要
A stacked MOS configuration for use in short channel length analog circuit technologies is provided. The stacked MOS configuration comprises a plurality of short-channel MOS transistors coupled in series and sharing a common gate terminal. In an embodiment, a first peripheral transistor provides a drain terminal for the stacked MOS configuration. A second peripheral transistor provides a source terminal for the stacked MOS configuration. Adjacent transistors in the stacked MOS configuration are connected in a drain-to-source configuration.
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