Net list generating method and layout designing method of semiconductor integrated circuit

摘要

A placement 103 of a macrocell is applied to a net list 102 formed by the logic synthesis by using the automatic layout tool, physical information of the macrocell is extracted in a physical information extracting step 104, and a net list 106 including the physical information is generated by attaching the extracted physical information to the instance name of the macrocell. Since the physical information such as placement coordinate, utilization factor, voltage drop value, and the like are attached to the instance name of the macrocell, the physical information can be grasped without reference to the layout data, and also analysis of the simulation and correction of the layout data can be facilitated. Also, since the placement position designation constraint is generated from the net list including the physical information, the high-quality layout design can be carried out.