Method of testing scan chain integrity and tester setup for scan block testing

摘要

A method of scan chain integrity testing for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) generating a partial shift test bench for the integrated circuit design wherein the partial shift test bench includes scan chains stitched together into shift registers and a scan block; (c) parallel loading the scan chains with a set of test vectors from the scan block with an offset of N bits wherein N is a number greater than one and less than the maximum length of the scan chains; (d) shifting the last N bits of the test vectors into the scan chains with N scan clock pulses; (e) comparing outputs of the scan chains with expected values in the scan block to produce a scan chain integrity test resu and (f) generating as output the scan chain integrity test result.