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Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
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机译:可变电压电源偏置以及基于负差分电阻(NDR)的存储设备的方法
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摘要
Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store operations to reduce power dissipation and improve reliability. Latch strength can also be increased to improve read speed, while latch strength can be reduced to improve write speed. In an SRAM cell including at least a negative differential resistance (NDR) device as a pull-up element, this type of latch control can be achieved through appropriate biasing of the NDR device(s). For example, drain-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength. Similarly, gate-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength.
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