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Data decision circuit using clock signal which has phase optimized with respect to phase of input data signal
Data decision circuit using clock signal which has phase optimized with respect to phase of input data signal
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机译:使用时钟信号的数据判决电路,该时钟信号的相位相对于输入数据信号的相位已优化
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摘要
In a data decision circuit: a clock generation unit generates a clock signal based on a phase difference signal so that the clock signal has an optimum phase with respect to a phase of an input data signal; a data determination unit determines data values carried by the input data signal, by using the clock signal; a phase-difference detection unit detects a rising-side phase difference and a falling-side phase difference, where the rising-side phase difference is a phase difference between a rising of the input data signal and a next transition in the clock signal, and the falling-side phase difference is a phase difference between the transition and a next falling of the input data signal; and a phase-difference-signal generation unit generates the phase difference signal so as to represent a difference between the rising-side phase difference and the falling-side phase difference.
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