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Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories
Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories
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机译:构建用于半导体存储器中软错误的优化SEC-DED代码和逻辑
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摘要
An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.
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