Refresh operation type semiconductor memory device capable of smoothly transferring special state to normal active state and its driving method

摘要

In a semiconductor memory device incorporating a memory core circuit requiring a refresh operation, a clock signal modifying circuit receives an external clock signal to generate a modified clock signal which is ineffective from a timing when the control is switched from an active mode to a special mode to a timing when at least one clock pulse time period of the external clock signal has passed after the control is switched from said special mode to an active mode. A forced refresh request signal generating circuit generates a forced refresh request signal at predetermined time periods and an internal clock signal having the same period as said forced refresh request signal. An all-time refresh request signal generating circuit generates an all-time refresh request signal in synchronization with the modified clock signal and the internal clock signal. A multiplexer selects the forced refresh request signal in the special mode and selects the all-time refresh request signal in the actual mode. A refresh pulse generating circuit generates a refresh pulse signal in accordance with one of the forced refresh request signal and the all-time refresh request signal selected by the multiplexer and transmits the refresh pulse signal to the memory core circuit. A read/write pulse generating circuit generates a read/write pulse signal in synchronization with the modified clock signal and transmits the read/write pulse signal to the memory core circuit.