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Large gain range, high linearity, low noise MOS VGA
Large gain range, high linearity, low noise MOS VGA
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机译:大增益范围,高线性度,低噪声MOS VGA
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摘要
An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
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机译:具有信道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。接收器前端提供可编程的衰减和可编程的增益低噪声放大器。集成在基板上的LC滤波器与镜像抑制混频器一起提供镜像频率抑制。整个温度范围内的滤波器调整和电感Q补偿均在芯片上执行。有源滤波器利用带屏蔽的多轨螺旋电感器来增加电路Q。频率规划可提供额外的镜像抑制能力。片内本地振荡器信号生成方法可减少失真。 PLL生成所需的带外LO信号。直接合成产生带内LO信号。 PLL VCO自动居中。差分晶体振荡器提供频率参考。使用整个接收器的差分信号传输。焊盘环和ESD夹紧结构提供ESD保护。分流器利用每个引脚的栅极升压来释放积累的ESD。 IF VGA利用交叉耦合差分对放大器实现的失真消除,交叉耦合差分对放大器的V ds Sub>与差分对源的电流控制一起动态修改。
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