Noise and linearity performances are critical characteristics for radio frequency integrated circuits( RFICs), especially for low noise amplifiers (LNAs) . In this paper, a detailed analysis of noise and lineaxity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the hnearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs,the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the hnearity performance separately, without trade-offs. The 1 .9 GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.
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