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Structure and method of vertical transistor DRAM cell having a low leakage buried strap
Structure and method of vertical transistor DRAM cell having a low leakage buried strap
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机译:具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法
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摘要
A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
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