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PROCESSOR WITH DEMAND-DRIVEN CLOCK THROTTLING POWER REDUCTION
PROCESSOR WITH DEMAND-DRIVEN CLOCK THROTTLING POWER REDUCTION
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机译:具有按需节流节流功率降低的处理器
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摘要
A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
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