HIGH SPEED ZERO DC POWER PROGRAMMABLE LOGIC DEVICE (PLD) ARCHITECTURE

摘要

A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells (Fig.3). Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit (330-333), a settable latch (320-323), a signal path means (360A, 360B), and an output logic gate (350). The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block (402-408) for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) (700) which includes an array of word lines (pwd) and bit lines (vcol, pcol) arranged in rows and columns for addressing, an array of OR gates (740), and a plurality of output logic circuits (750).