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Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same
Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same
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机译:每个栅极具有两个捕获位置的电荷捕获非易失性存储器及其操作方法
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摘要
A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.
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