Semiconductor Device Having Well Structure For Improving Soft Error Rate Immunity And Latch-up Immunity And Fabrication The Same

摘要

It provides a semiconductor device and its manufacturing method having a well structure to improve the soft error rate resistance and the latch-up immunity. The device is provided with a second well of the first wells and the second conductive type of a first conductivity type formed in a semiconductor substrate of a first conductivity type. The second well, the first claim Mohs PET of the first conductivity type having a source / drain of the conductivity type are formed, Mohs PET of the second conductivity type having a first source / drain of the conductivity type, the first well are formed do. While following of the first well, the second drain region of the conductivity type below the Mohs PET, the third well of the second conductivity type is formed. The first well can be connected to said semiconductor substrate between said third wells.