首页> 外国专利> Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same

Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same

机译:具有数据输入/输出电路的半导体存储装置及其测试方法,该数据输入/输出电路能够减少存储器测试期间的数据写入次数

摘要

PURPOSE: A semiconductor memory device and a test method thereof are provided to reduce the number of data writing during a memory test so that the test time is reduced. CONSTITUTION: A semiconductor memory device includes a bank selection signal generator(30), a bank connector and a column selector. The bank selection signal generator(30) of 3 parts(32,34,36) generates a bank selection signal for connecting bit lines of banks to data input/output lines. The bank connector selects at least two banks during write operation, selects a bank during read operation, and connect bit lines of a selected bank to a first data lines. The column selector connects a data line of the first data lines to the data input/output line, according to each column-line selection signal of bit-line address. Thereby, the number of data writing during a memory test can be reduced.
机译:目的:提供一种半导体存储器件及其测试方法,以减少存储器测试期间的数据写入次数,从而减少了测试时间。组成:一种半导体存储器件,包括一个存储体选择信号发生器(30),一个存储体连接器和一个列选择器。 3部分(32、34、36)的存储体选择信号发生器(30)产生用于将存储体的位线连接到数据输入/输出线的存储体选择信号。存储体连接器在写入操作期间选择至少两个存储体,在读取操作期间选择存储体,并将所选存储体的位线连接到第一数据线。列选择器根据位线地址的每个列线选择信号将第一数据线的数据线连接到数据输入/输出线。由此,可以减少存储器测试期间的数据写入次数。

著录项

  • 公开/公告号KR100574918B1

    专利类型

  • 公开/公告日2006-05-02

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR19990019983

  • 发明设计人 장태성;

    申请日1999-06-01

  • 分类号G11C29;

  • 国家 KR

  • 入库时间 2022-08-21 21:23:53

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