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Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same
Semiconductor memeory device having data input/output circuit capable of reducing data writing number during memory test and the test method of the same
PURPOSE: A semiconductor memory device and a test method thereof are provided to reduce the number of data writing during a memory test so that the test time is reduced. CONSTITUTION: A semiconductor memory device includes a bank selection signal generator(30), a bank connector and a column selector. The bank selection signal generator(30) of 3 parts(32,34,36) generates a bank selection signal for connecting bit lines of banks to data input/output lines. The bank connector selects at least two banks during write operation, selects a bank during read operation, and connect bit lines of a selected bank to a first data lines. The column selector connects a data line of the first data lines to the data input/output line, according to each column-line selection signal of bit-line address. Thereby, the number of data writing during a memory test can be reduced.
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