首页> 外国专利> Poly-Si TFT-LCD array substrate fabrication method using FALC process

Poly-Si TFT-LCD array substrate fabrication method using FALC process

机译:利用FALC工艺的多晶硅薄膜晶体管液晶显示器阵列基板的制造方法

摘要

invention FALC process for using a low temperature poly-Si TFT-LCD array substrate manufacturing method as in the related, and more particularly to a method that can minimize the crystallization time of the TFT channel region. Conventional crystallization method in the crystallization time, given the way that by performing the heat treatment yieoteuna applying an electric field directly to the source region and the drain region of the amorphous silicon thin film within each of the TFT array on a substrate and crystallizing the amorphous silicon thin film at the same time, mass production The minimization problem remained zero line results. The production method of the present invention is to solve this problem, by the direct electric field in parallel with the source region and the drain region during heat treatment for crystallization is applied to the common gate signal line connected to the gate electrode of each TFT is a voltage higher than a threshold voltage , to increase the strength of the current flowing through the channel region larger than if only the existing electric field was applied, which is the main feature is to minimize the crystallisation time of the TFT with the channel region.
机译:本发明的FALC工艺,其使用如相关技术中的低温多晶硅TFT-LCD阵列基板的制造方法,并且更具体地,涉及一种可以使TFT沟道区的结晶时间最小化的方法。结晶时间中的常规结晶方法,该方法是通过进行热处理yieoteuna,将电场直接施加到基板上每个TFT阵列内的非晶硅薄膜的源区和漏区,并使非晶质结晶硅薄膜同时批量生产最小化问题仍然是零线结果。本发明的生产方法是为了解决该问题,通过在结晶化热处理期间将与源区和漏区平行的直流电场施加到与每个TFT的栅极相连的公共栅极信号线上。高于阈值电压的电压,以增加流过沟道区的电流的强度,使其比仅施加现有电场时更大,这主要是为了使具有沟道区的TFT的结晶时间最小化。

著录项

  • 公开/公告号KR100605268B1

    专利类型

  • 公开/公告日2006-07-26

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20030080822

  • 申请日2003-11-15

  • 分类号G02F1/136;

  • 国家 KR

  • 入库时间 2022-08-21 21:23:19

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