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Method and device for optimizing the performance of the register transmission level, in particular with interference pulse analysis and reduction
Method and device for optimizing the performance of the register transmission level, in particular with interference pulse analysis and reduction
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机译:用于优化寄存器传输级别的性能的方法和设备,尤其是通过干扰脉冲分析和减少来优化的方法和设备
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摘要
A method and apparatus for design-for-low-power of register transfer level (RTL) controller/data path circuits that implement control-flow intensive specifications. The method of the invention focuses on multiplexer networks and registers which dominate the total circuit power consumption and reduces generation and propagation of glitches in both the control and data path parts of the circuit. Further the method reduces glitching power consumption by minimizing propagation of glitches in the RTL circuit through restructuring multiplexer networks (to enhance data correlations and eliminate glitchy control signals), clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. To reduce power consumption in registers, the clock inputs to registers are gated with conditions derived by an analysis of the RTL circuit, ensuring that glitches are not introduced on the clock signals.
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