Field effect transistor, transistor arrangement, as well as a process for the preparation of a semiconducting silicon monocrystalline substrate and a transistor arrangement

摘要

For the insulation of active regions of n - fets (91) and p - fets (92), in addition to the portions of a semiconductor substrate (1) designed active areas (11n, 11p) insulator structures (21n, 21p, 22n, 22p) in the semiconductor substrate (1) is provided, which as a consequence of the tensile stress or a compressive stress on the respectively adjacent active regions (11n, exert 11p), and this correspondingly bracing. The insulator structures (21n, 21p, 22n, 22p) are in each case based on a base portion (211), through which in adjacent active regions (21n), a tensile stress is induced. In each case to a p - fet (92) subsequent insulator structures (21p, 22p) are selectively with additional buffer layers (61), through which a compressive stress is induced in the adjacent structures. The charge carrier mobility, as well as of electrons in the channel regions (112n) of the n - fets (91) as well as the holes in the channel regions (112p) of the p - fets (92) is increased and the functionality of both of the n - fets (91) as well as of the p - fets (92) improved.