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Phase locked loop integrated circuit generates clock signal at output terminal and varies capacitance of output terminal concurrently with changing frequency of clock signal
Phase locked loop integrated circuit generates clock signal at output terminal and varies capacitance of output terminal concurrently with changing frequency of clock signal
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机译:锁相环集成电路在输出端子处产生时钟信号,并随着时钟信号的频率变化而同时改变输出端子的电容。
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摘要
A voltage controlled oscillator (VCO) generates a clock signal at an output terminal in response to control signals generated based on UP and DOWN pumping signals, and varies the capacitance of the output terminal concurrently with changing frequency of the clock signal. An independent claim is also included for phase locked loop device.
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