Phase-shift resistant frequency variable clock-pulse generator for semiconductor devices, has external clock output circuit for generating an external clock-signal from the divided clock-signal

摘要

Reduction in the clock-pulse frequency at which semiconductor devices are clocked results in savings in power of these devices but requires a clock- pulse generator designed with a frequency divider (11) for outputting a divided clock-signal by dividing an input signal in concordance with a divider ratio control signal. An external clock output circuit (13) generates an external clock-signal from the divided clock-signal, and an internal clock output circuit (15) generates an internal clock signal from the divided clock-signal, the phase of which is adjusted to that of the external clock-signal by a phase-setting circuit (15,18). A divider ratio control-signal blocking-circuit (33) deactivates the divider ratio control signal while a clocking signal is operative, so as to generate a given clock-pulse signal while the divider ratio control signal is deactivated and for changing the frequency of the divided clock-pulse signal.