首页>
外国专利>
procedures with reduced maskenzahl for the manufacture of mischsspannung cmos transistors with high performance and i / o transistors of high reliability
procedures with reduced maskenzahl for the manufacture of mischsspannung cmos transistors with high performance and i / o transistors of high reliability
展开▼
机译:具有降低的遮罩效应的程序,用于制造高性能的混合晶体管和高可靠性的I / O晶体管
展开▼
页面导航
摘要
著录项
相似文献
摘要
A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors. IMAGE IMAGE
展开▼