Being layout wiring manner of the standard electrolysis cell or the semiconductor integrated circuit, and its layout

摘要

PROBLEM TO BE SOLVED: To provide a functional standard cell including a bypass capacitor, which has small residual inductance and provides an enough capacity without enlarging an area for eliminating power supply noise of a high frequency element, and a semiconductor integrated circuit having it, and its arrangement wiring method.;SOLUTION: A standard cell with a multilayer wiring layer has a semiconductor substrate, wherein at least one functional circuit element comprising input and output signal terminals is formed, a signal wiring layer, which is formed above a semiconductor substrate and composed of at least one layer for wiring input and output signal terminals and a three-terminal capacitor formed above a signal wiring layer. The three-terminal capacitor has a power supply wiring layer and first and second ground wiring layers holding a power supply wiring layer between via an insulation layer. A functional circuit element receives power from the power supply wiring layer and a first ground wiring layer.;COPYRIGHT: (C)2003,JPO