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Digital VCO, VCO circuit, PLL circuit, information recording device and synchronous clock signal generating method
Digital VCO, VCO circuit, PLL circuit, information recording device and synchronous clock signal generating method
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机译:数字VCO,VCO电路,PLL电路,信息记录装置及同步时钟信号生成方法
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摘要
A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.
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