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16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits

机译：16.6具有同步数字电路的CmOs混合信号集成电路中降低基板噪声的方法和实验验证

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Mustafa Badaroglu; Marc Van Heijningen; Vincent Gravot; John Compiet; Stéphane Donnay; Marc Engels; Georges Gielen; Hugo De Man;
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年度 2008
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1. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J] . Badaroglu M., van Heijningen M., Gravot V., IEEE Journal of Solid-State Circuits . 2002,第11期

机译：具有同步数字电路的CMOS混合信号IC中降低基板噪声的方法和实验验证
2. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J] . Badaroglu M., van Heijningen M., Gravot V., IEEE Journal of Solid-State Circuits . 2002,第11期

机译：具有同步数字电路的CMOS混合信号IC中降低基板噪声的方法和实验验证
3. An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits [J] . Miguel A. Mendez, Jose Luis Gonzalez, Diego Mateo, Microelectronics journal . 2005,第1期

机译：混合信号CMOS集成电路中数字电路特性与电源噪声谱之间关系的研究
4. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [C] . Badaroglu, M., van Heijningen, . 2002

机译：具有同步数字电路的CMOS混合信号IC中降低基板噪声的方法和实验验证
5. Concurrent substrate coupling noise modeling and active noise reduction methodology for mixed-signal physical design. [D] . Liu, Tingyang. 1999

机译：并行基板耦合噪声建模和主动降噪方法，用于混合信号物理设计。
6. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors [O] . Shoji Kawahito, Min-Woong Seo 2014

机译：用于超低噪声CMOS图像传感器的基于多采样的信号读取电路的降噪效果
7. Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients [O] . Badaroglu Mustafa, Tiri Kris, Donnay Stephane, 2002

机译：同步CMOS数字电路中的时钟树优化，可通过折叠电源电流瞬变来降低基板噪声

16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits

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