Output stage interface circuit for outputting digital data onto a data bus, and a method for operating an output stage interface circuit

摘要

An output stage interface circuit (50) implemented on a P-substrate comprises a first substrate diffusion isolated main NMOS transistor (MN1) coupling a data output terminal (5) to a first rail (2) which is held at ground, and a second main PMOS transistor MP2 coupling the data output terminal (5) to a second rail (3) to which the power supply voltage V_DD is applied. First and second data control signals on first and second data control lines (8) and (9) through first and second primary and secondary buffer circuits (11, 14, 12, 15) selectively operate the first main transistor MN1 and the second main transistor MP2 for determining the logic high and low states of the data output terminal (5). A first node (28), to which an independently configurable back gate (24) of the first main transistor MN1 and the first primary buffer circuit (11) are coupled, is selectively and alternately coupleable to one of the first rail (2) and the data output terminal (5) by a first switch circuit (29) in response to the voltage on the data output terminal (5), so that when the voltage on the data output terminal (5) is pulled below a first voltage reference (V_REF1) which is less than a diode voltage drop below ground, the first node (28) is coupled to the data output terminal (5) for preventing a parasitic bipolar transistor Q_p1 and parasitic diode D_p2 of the first main transistor MN1 sourcing current to the data bus, and also for holding the first main transistor MN1 in the off-state. A second switch circuit (61) selectively and alternately couples a second node (59), to which an independently configurable back gate (51) of the second main transistor MP2 and the second primary buffer circuit (14) are coupled, to one of the second rail (3) and the data output terminal (5), so that when the voltage and the data output terminal (5) is pulled above a second voltage reference (V_REF2) which is less than a diode voltage drop above V_DD, the second node (59) is coupled to the data output terminal (5) for preventing a parasitic bipolar transistor Q_p3 and a parasitic diode D_p4 of the second main transistor MP2 sourcing current from the data bus, and also for holding the second main transistor MP₂ in the off-state.