METHOD FOR MODELING METASTABILITY DECAY USING FENCE LOGIC INSERTION

摘要

A method for modeling metastablilty decay in digital circuit devices includes identifying each latch at a receiving end of an asynchronous clock boundary, enumerating a latch depth for each latch within logical influence of each of the identified receive latches, and inserting fence logic immediately prior to the input of each latch at an enumerated depth, n, wherein n represents a latch depth at which an indeterminate metastable value received at the asynchronous boundary decays to a random logic value. The fence logic converts an identified indeterminate value to a random logic value, and any indeterminate value initially received is allowed to propagate up to the fence logic.