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Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
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机译:用于DRAM中DDR1和DDR2操作模式的每I / O线两位数据写入总线
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摘要
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.
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