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Method for designing a semiconductor device capable of reflecting a time delay effect for dummy metal fill
Method for designing a semiconductor device capable of reflecting a time delay effect for dummy metal fill
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机译:设计能够反映虚拟金属填充物的时间延迟效应的半导体器件的方法
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摘要
Disclosed is a method for designing a semiconductor device. In an existing semiconductor design, a time delay effect caused by a dummy metal interconnection cannot be reflected. In order to address this disadvantage, a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic extract step such that a time delay effect caused by the dummy metal pattern in semiconductor design is reflected. Accordingly, a semiconductor device can be designed by effectively reflecting a time delay effect. According to the method, since a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic extract step so that resistor capacitance values of interconnections (including dummy interconnections) between logic elements are extracted, it is possible to more exactly design a semiconductor device by tacking a time delay effect into account.
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