首页>
外国专利>
Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits
Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits
展开▼
机译:低功率,高SNR,高阶delta sigma调制器级,具有带流水线交叉耦合输入电路的积分器
展开▼
页面导航
摘要
著录项
相似文献
摘要
In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.
展开▼