Circuit for producing a variable frequency clock signal having a high frequency low jitter pulse component

摘要

Embodiments of the present invention include first and second pulse trains input to a switch in synchronization. The first and second pulse trains may have a repeating high and low values at first and second frequencies, respectively, and the first pulse train may transition from the low to the high value with a first edge sharpness. The second pulse train input may have a lower than the first frequency. The switch may use a selection signal in synchronization with the first pulse train to select an output from the first or second pulse train to create an output pulse train appropriate to transition fault test an integrated circuit. The switch may switch from the second pulse train to the first pulse train and substantially maintain the first edge sharpness of the first pulse train during a low value of both the first and second pulse trains.