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Clock control circuit and clock control method that switchingly supplies a high-speed clock and a low-speed clock

机译:切换提供高速时钟和低速时钟的时钟控制电路和时钟控制方法

摘要

In this clock control circuit and this clock control method, during a standby-mode of a CPU, a low-speed clock is supplied. Processings including timer processing and receiving processing are carried out by low-speed operation at the CPU. When an interrupt signal is inputted to the CPU which is in the standby mode, a high-speed clock source is activated, and counting of the low-speed clock is started at a counter. When a count value of the counter reaches a set value of a register, a high-speed clock is selected by a selection signal. The high-speed clock is supplied to the CPU, and interruption processing is started.
机译:在该时钟控制电路和该时钟控制方法中,在CPU的待机模式期间,提供低速时钟。包括定时器处理和接收处理的处理是通过CPU的低速操作执行的。当将中断信号输入到处于待机模式的CPU时,将激活高速时钟源,并在计数器处开始对低速时钟进行计数。当计数器的计数值达到寄存器的设定值时,通过选择信号选择高速时钟。高速时钟被提供给CPU,并开始中断处理。

著录项

  • 公开/公告号US7293185B2

    专利类型

  • 公开/公告日2007-11-06

    原文格式PDF

  • 申请/专利权人 YOSHINORI SHIMOSAKODA;

    申请/专利号US20040784783

  • 发明设计人 YOSHINORI SHIMOSAKODA;

    申请日2004-02-24

  • 分类号G06F1/32;

  • 国家 US

  • 入库时间 2022-08-21 21:00:58

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