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CLOCK SUPPLY CONTROL SYSTEM, DESIGNING METHOD FOR CLOCK SUPPLY CONTROL CIRCUIT AND RECORD MEDIUM RECORDED WITH DESIGN PROGRAM FOR CLOCK SUPPLY CONTROL CIRCUIT
CLOCK SUPPLY CONTROL SYSTEM, DESIGNING METHOD FOR CLOCK SUPPLY CONTROL CIRCUIT AND RECORD MEDIUM RECORDED WITH DESIGN PROGRAM FOR CLOCK SUPPLY CONTROL CIRCUIT
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机译:时钟供应控制系统,时钟供应控制电路的设计方法以及记录有时钟供应控制电路的设计程序的记录介质
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摘要
PROBLEM TO BE SOLVED: To provide a clock supply control system capable of easily and automatically designing a gated clock, with which the characteristics of minimizing a clock skew and suppressing increase in the signal delay of an enable signal are satisfied, in a short time in gated clock design under the control of a multi- input/multi-stage enable buffer.;SOLUTION: At least one two-input buffer for inputting a clock signal and the output signal of a gating circuit is inserted on the post-stage of the gating circuit directly driving an element to supply a clock and by connecting a fixed value signal to a terminal, to which the clock signal is directly connected, inside the gating circuit, to which the clock signal is directly connected, logically equivalent conversion is performed.;COPYRIGHT: (C)2001,JPO
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