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Test structures in unused areas of semiconductor integrated circuits and methods for designing the same

机译:半导体集成电路未使用区域中的测试结构及其设计方法

摘要

The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.
机译:本发明是半导体集成电路的未使用区域中的测试结构及其设计方法。在本发明的示例性方面,一种用于在半导体集成电路中放置测试结构的方法包括:(a)检测半导体集成电路中的虚设区域,该半导体集成电路包括在顶部金属层上的探针垫;以及(b)用有源测试单元填充虚拟区域,有源测试单元彼此连接; (c)用金属线将每个有源测试单元连接到探针垫。

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