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Latch-type sense amplifier

机译:锁存型读出放大器

摘要

An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.
机译:一种改进的锁存型读出放大器电路,具有形成锁存器的两个交叉耦合的反相器,用于将锁存器选择性地连接到电源的电源耦合装置以及用于将每个反相器的输入选择性地连接到互补位的位线耦合电路内存阵列中的一行。该电路被配置为通过提供延迟的读出放大器使能信号通过晶体管以延迟位线从读出放大器的断开直到锁存动作完成,并在其中添加两个晶体管,从而以提高的可靠性来感测位线之间的电压差。与常规锁存器的现有晶体管串联,以校正锁存器的反相器的阈值电压之间的偏移。

著录项

  • 公开/公告号US7227798B2

    专利类型

  • 公开/公告日2007-06-05

    原文格式PDF

  • 申请/专利权人 ANUJ GUPTA;SANJEEV CHOPRA;

    申请/专利号US20030679941

  • 发明设计人 SANJEEV CHOPRA;ANUJ GUPTA;

    申请日2003-10-06

  • 分类号G11C7/00;

  • 国家 US

  • 入库时间 2022-08-21 21:00:23

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