首页> 外国专利> Latch-type sense amplifier for a non-volatile memory with reduced margin between supply voltage and bitline-selection voltage

Latch-type sense amplifier for a non-volatile memory with reduced margin between supply voltage and bitline-selection voltage

机译:用于非易失性存储器的锁存型读出放大器,电源电压和位线选择电压之间的余量降低

摘要

A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.
机译:公开了一种读出放大器和用于访问存储器设备的方法。 在一个实施例中,用于存储器件的读出放大器包括通过第一局位位线和第一主位线选择性地耦合到第一存储器单元的第一输入节点,第二输入节点通过第二本地位线和第二主位线选择性地耦合到 第二存储器单元或被配置为生成参考电流的参考生成器,第一电流发生器可控制,以便将第一可变电流注入第一输入节点,第二电流发生器可控制,以便将第二可变电流注入到其中 第二输入节点,耦合到第一输入节点的第一分支,包括第一开关电路,第一感测晶体管和第一锻造晶体管和耦合到第二输入节点的第二分支,包括第二读取晶体管第二开关电路 和第二强制晶体管。

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