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Address coding method and address decoder for reducing sensing noise during refresh operation of memory device

机译:用于减少存储设备的刷新操作期间的感测噪声的地址编码方法和地址解码器

摘要

An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.
机译:由包括分别由至少两个存储块共享的多个存储体的存储设备执行的地址编码方法,包括:在存储设备的刷新操作期间激活由至少两个存储块共享的相邻存储体,并且使能每个存储体中的刷新操作在至少两个存储块之间交替进行。该方法包括在存储设备的另一操作期间激活由至少两个存储块共享的相邻存储体,以及在至少两个存储块之间交替地启用每个存储体中的另一操作。

著录项

  • 公开/公告号US7180816B2

    专利类型

  • 公开/公告日2007-02-20

    原文格式PDF

  • 申请/专利权人 CHUL-WOO PARK;

    申请/专利号US20050152449

  • 发明设计人 CHUL-WOO PARK;

    申请日2005-06-14

  • 分类号G11C8/00;

  • 国家 US

  • 入库时间 2022-08-21 21:00:22

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