首页> 外国专利> CARRY-SKIP ADDER HAVING MERGED CARRY-SKIP CELLS WITH SUM CELLS

CARRY-SKIP ADDER HAVING MERGED CARRY-SKIP CELLS WITH SUM CELLS

机译:随身携带的购物者将随身携带的随身携带的细胞合并

摘要

A multi-bit adder includes a carry chain, a carry-skip network, sum cells, anda carry-sum cell. The carry chain propagates, generates, or kills carry-in bits.The carry-skip network is coupled to the carry chain to selectively skip the carry-inbits over at least one portion of the carry chain. The sum cells are coupled alongthe carry chain to sum the carry-in bits with corresponding bits of two operandsto generate a multi-bit resultant. The carry-sum cell is coupled to receive oneof the carry-in bits to a single intermediate bit position on the carry chain andto generate one bit of the multi-bit resultant having a more significant bit positionthan the single intermediate bit position.
机译:多位加法器包括进位链,进位跳过网络,求和单元和一个进位求和单元。进位链传播,生成或杀死进位位。进位跳过网络耦合到进位链,以有选择地跳过进位位至少在进位链的一部分上。总和单元沿着进位链,将进位位与两个操作数的对应位相加生成多位结果。进位求和单元耦合以接收一个进位位到进位链上单个中间位的位置,以及生成位位置更高的多位结果的一位而不是单个中间位的位置。

著录项

  • 公开/公告号SG129668A1

    专利类型

  • 公开/公告日2007-03-20

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号SG2007008311

  • 发明设计人 WIJERATNE SAPUMAL;

    申请日2005-07-15

  • 分类号G06F7/50;

  • 国家 SG

  • 入库时间 2022-08-21 20:55:51

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