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An inductor or low loss interconnect in an integrated circuit

机译:集成电路中的电感器或低损耗互连

摘要

An integrated circuit with a buried layer (e.g., 105) for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried layer (e.g., 105) formed between less doped layers. This provides a high Q inductor while preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer (e.g., 130) in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.
机译:具有用于增加形成在集成电路中的电感器的Q的掩埋层(例如105)的集成电路。衬底包括形成在较少掺杂层之间的高掺杂掩埋层(例如105)。这样可在保持器件和锁存特性的同时提供高Q电感。电感器还可以在电感器中包括增加厚度的导电层(例如130),以进一步增加Q。本发明还针对低损耗互连。

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