首页> 外国专利> DUAL BIT MULTI-LEVEL BALLISTIC MONOS MEMORY, AND MANUFACTURING METHOD, PROGRAMMING, AND OPERATION PROCESS FOR THE MEMORY

DUAL BIT MULTI-LEVEL BALLISTIC MONOS MEMORY, AND MANUFACTURING METHOD, PROGRAMMING, AND OPERATION PROCESS FOR THE MEMORY

机译:双比特多级弹道记忆存储器及其制造方法,编程和操作过程

摘要

In this invention, a fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is disclosed with a two or three polysilicon split gate side wall process and it operation. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel. The cell structure is realized by (i) placing side wall control gates (240) over a composite of Oxide-Nitride-Oxide (ONO) (230) on both sides of the word gate (245), and (ii) forming the control gates and bit impurity layer by self-alignment and sharing the control gates and bit impurity layers between neighboring memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the impurity layer.
机译:在本发明中,公开了一种快速低压弹道程序,超短通道,超高密度,双位多级闪存,其具有两个或三个多晶硅分裂栅侧壁工艺及其操作。本发明的结构和操作是通过具有超短控制栅沟道的双MONOS单元结构实现的。单元结构是通过(i)将侧壁控制栅(240)放置在字栅(245)两侧的氧化物-氮化物-氧化物(ONO)(230)的复合材料上,以及(ii)形成控制结构来实现的栅和位杂质层通过自对准并在相邻存储单元之间共享控制栅和位杂质层以实现高密度。此过程中使用的关键元素是:1)一次性侧壁工艺,以制造具有或不具有阶梯结构的超短沟道和侧壁控制栅,以及2)在氮化物和氮化物上自对准定义控制栅。杂质层。

著录项

  • 公开/公告号EP1345273A4

    专利类型

  • 公开/公告日2007-05-09

    原文格式PDF

  • 申请/专利权人 HALO LSI INC.;

    申请/专利号EP20010997853

  • 发明设计人 OGURA TOMOKO;HAYASHI YUTAKA;OGURA SEIKI;

    申请日2001-11-21

  • 分类号H01L21/28;H01L21/8247;H01L21/8246;H01L27/115;H01L29/788;H01L29/792;

  • 国家 EP

  • 入库时间 2022-08-21 20:49:35

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