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2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND /BL
2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND /BL
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机译:使用BL和/ BL之间的定义电荷交换的2T2C信号保证金测试模式
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摘要
The present invention provides at test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
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