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MRAM ARCHITECTURE WITH A GROUNDED WRITE BIT LINE AND ELECTRICALLY ISOLATED READ BIT LINE

机译:具有接地写入位线和电气隔离的读取位线的MRAM体系结构

摘要

Each memory cell of a magnetoresistive random access memory (MRAM) array has a magnetoresistive tunnel junction (MTJ) and a transistor coupled to the MTJ. Writing, occurs by write lines along rows and columns of the array. One set of the write lines is connected to the end of the MTJs that is not connected to the transistors. These write lines are thereby close to the MTJs and thus have good magnetic coupling to the MTJs, which is important in keeping write current low. These write lines are driven on one end by drivers. Sensing on the other hand occurs on a read bit line that is coupled to the end of the transistor of the memory cell that is not coupled to the MTJ. By having the sense amplifier(s) on a different line from the write drivers, sensing is not slowed by the capacitance of the write drivers.
机译:磁阻随机存取存储器(MRAM)阵列的每个存储单元具有磁阻隧道结(MTJ)和耦合至MTJ的晶体管。写入是通过沿阵列的行和列写线而发生的。一组写线连接到未连接到晶体管的MTJ的一端。这些写线因此靠近MTJ,因此与MTJ具有良好的磁耦合,这对于保持低写电流很重要。这些写线由驱动器一端驱动。另一方面,感测发生在读取位线上,该读取位线上耦合到未耦合到MTJ的存储单元晶体管的一端。通过将一个或多个读出放大器置于与写驱动器不同的线上,不会因写驱动器的电容而减慢检测速度。

著录项

  • 公开/公告号EP1588372B1

    专利类型

  • 公开/公告日2007-08-08

    原文格式PDF

  • 申请/专利权人 FREESCALE SEMICONDUCTOR INC.;

    申请/专利号EP20040702960

  • 发明设计人 NAHAS JOSEPH J.;

    申请日2004-01-16

  • 分类号G11C11;G11C11/16;

  • 国家 EP

  • 入库时间 2022-08-21 20:48:40

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