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NANOWIRE DEVICE WITH (111) VERTICAL SIDEWALLS AND METHOD OF FABRICATION

机译:具有(111)个垂直侧壁的纳米装置及其制造方法

摘要

A nano-scale device 10, 20, 30, 60 and method 40, 50, 70 of fabrication provide a nanowire 14, 24, 34, 64 having (111) vertical sidewalls 14a, 22e, 34a, 64a. The nano-scale device includes a semiconductor-on-insulator substrate 12, 22, 32, 62 polished in a [110] direction, the nanowire, and an electrical contact 26, 35 at opposite ends of the nanowire 24, 34. The method 40, 50, 70 includes wet etching 42, 52, 72 a semiconductor layer 12a, 22a, 32a. 62a of the semiconductor-on-insulator substrate to form 44, 54 the nanowire 24, 34 extending between a pair of islands 22f, 32f in the semiconductor layer 22a, 32a. The method 50 further includes depositing 56 an electrically conductive material on the pair of islands to form the electrical contacts 26, 36. A nano-pn diode 60 includes the nanowire 64 as a first nano-electrode, a pn-junction 66 verically stacked on the nanowire 64, and a second nano-electrode 68 on a (110) horizontal planar end of the pn-junction. The nano-pn diode 60 may be fabricated in array of the diodes on the semiconductor-on-insulator substrate 62.
机译:纳米级装置10、20、30、60和制造方法40、50、70提供了具有(111)个垂直侧壁14a,22e,34a,64a的纳米线14、24、34、64。纳米级装置包括沿[110]方向抛光的绝缘体上半导体衬底12、22、32、62,纳米线以及在纳米线24、34的相对端的电触点26、35。图40、50、70包括湿法刻蚀42、52、72,半导体层12a,22a,32a。绝缘体上半导体衬底62a形成纳米线24、34,纳米线24、34在半导体层22a,32a中的一对岛22f,32f之间延伸。方法50还包括在一对岛上沉积56导电材料以形成电触点26、36。纳米pn二极管60包括作为第一纳米电极的纳米线64,在其上垂直堆叠的pn结66。纳米线64和在pn结的(110)水平平面端上的第二纳米电极68。可以在绝缘体上半导体衬底62上以二极管的阵列制造纳米pn二极管60。

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