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MATCHED NAND AND NOR GATES HAVING IDENTICAL OUPUT CHARACTERISTICS AND OUPUT BUFFER USING THE SAME

机译:具有相同输出特性和使用相同输出缓冲的匹配门与非门

摘要

A NAND and NOR gates matched to have identical output characteristics and an output buffer using the same are provided to reduce skew of an output signal by making the output characteristics of the NAND and NOR gates according to the change of first and second input signals identical. A NAND gate(410) receives first and second input signals. A NOR gate receives third and fourth input signals. A pull-up transistor is connected between a power supply voltage and an output signal, and has a gate connected to an output of the NAND gate. A pull-down transistor is connected between a ground voltage and an output signal, and has a gate connected to an output of the NOR gate. The NAND gate comprises a first transistor having a source connected to a power supply voltage and a gate connected to a ground voltage, second to fourth transistors connected between the first PMOS transistor and the ground voltage, and fifth to seventh transistors connected between the first transistor and the ground voltage. The first input signal is connected to gates of the second, third and seventh transistors. The second input signal is connected to gates of the fourth to sixth transistors. The output of the NAND gate is generated by connecting drains of the second and third transistors and drains of the fifth and sixth transistors. The NOR gate comprises eighth to tenth transistors connected to the power supply voltage, eleventh to thirteenth transistors connected to the power supply voltage, and a fourteenth transistor connected among the tenth and thirteenth transistors and the ground voltage and having a gate connected to the power supply voltage. The third input signal is input to gates of the eighth, tenth and twelfth transistors. The fourth input signal is input to gates of the ninth, eleventh and thirteenth transistors. The output of the NOR gate is generated by connecting drains of the ninth and tenth transistors and drains of the twelfth and thirteenth transistors.
机译:提供匹配以具有相同输出特性的NAND和NOR门以及使用它们的输出缓冲器,以通过根据第一和第二输入信号的变化使NAND和NOR门的输出特性相同来减少输出信号的偏斜。与非门(410)接收第一和第二输入信号。或非门接收第三和第四输入信号。上拉晶体管连接在电源电压和输出信号之间,并且其栅极连接到与非门的输出。下拉晶体管连接在地电压和输出信号之间,并且其栅极连接到或非门的输出。 NAND门包括:第一晶体管,其源极连接到电源电压;栅极连接到地电压;第二至第四晶体管,连接在第一PMOS晶体管和地电压之间;第五至第七晶体管,连接在第一晶体管之间。和接地电压。第一输入信号连接到第二,第三和第七晶体管的栅极。第二输入信号连接到第四至第六晶体管的栅极。通过将第二晶体管和第三晶体管的漏极与第五晶体管和第六晶体管的漏极连接来产生与非门的输出。或非门包括连接到电源电压的第八至第十晶体管,连接到电源电压的第十至第十三晶体管,以及连接在第十和第十三晶体管与接地电压之间并具有连接至电源的栅极的第十四晶体管。电压。第三输入信号被输入到第八,第十和第十二晶体管的栅极。第四输入信号被输入到第九,第十一和第十三晶体管的栅极。 NOR门的输出是通过将第九和第十晶体管的漏极与第十二和第十三晶体管的漏极连接而产生的。

著录项

  • 公开/公告号KR100660867B1

    专利类型

  • 公开/公告日2006-12-26

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20050054363

  • 发明设计人 LEE WOO JIN;KIM SUNG HOON;

    申请日2005-06-23

  • 分类号G11C7/10;

  • 国家 KR

  • 入库时间 2022-08-21 20:39:24

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