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MATCHED NAND AND NOR GATES HAVING IDENTICAL OUPUT CHARACTERISTICS AND OUPUT BUFFER USING THE SAME
MATCHED NAND AND NOR GATES HAVING IDENTICAL OUPUT CHARACTERISTICS AND OUPUT BUFFER USING THE SAME
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机译:具有相同输出特性和使用相同输出缓冲的匹配门与非门
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摘要
A NAND and NOR gates matched to have identical output characteristics and an output buffer using the same are provided to reduce skew of an output signal by making the output characteristics of the NAND and NOR gates according to the change of first and second input signals identical. A NAND gate(410) receives first and second input signals. A NOR gate receives third and fourth input signals. A pull-up transistor is connected between a power supply voltage and an output signal, and has a gate connected to an output of the NAND gate. A pull-down transistor is connected between a ground voltage and an output signal, and has a gate connected to an output of the NOR gate. The NAND gate comprises a first transistor having a source connected to a power supply voltage and a gate connected to a ground voltage, second to fourth transistors connected between the first PMOS transistor and the ground voltage, and fifth to seventh transistors connected between the first transistor and the ground voltage. The first input signal is connected to gates of the second, third and seventh transistors. The second input signal is connected to gates of the fourth to sixth transistors. The output of the NAND gate is generated by connecting drains of the second and third transistors and drains of the fifth and sixth transistors. The NOR gate comprises eighth to tenth transistors connected to the power supply voltage, eleventh to thirteenth transistors connected to the power supply voltage, and a fourteenth transistor connected among the tenth and thirteenth transistors and the ground voltage and having a gate connected to the power supply voltage. The third input signal is input to gates of the eighth, tenth and twelfth transistors. The fourth input signal is input to gates of the ninth, eleventh and thirteenth transistors. The output of the NOR gate is generated by connecting drains of the ninth and tenth transistors and drains of the twelfth and thirteenth transistors.
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