WAFER-LEVEL PACKAGE AND METHOD FOR FABRICATING THE WAFER-LEVEL PACKAGE

摘要

The present invention is a preliminary test (PT) and a final test (FT) relates to a method for manufacturing a semiconductor device using a wafer-level package and the wafer-level package is carried out, the task of planning the reduction of the increase and manufacturing costs of production efficiency It shall be. ; A plurality of semiconductor chip circuit forming region 12 (circuit region), the plurality of chip terminals 13 and the semiconductor wafer 11 to be formed, drawing out the chip terminals to the chip terminal forming position and the other position, and at the same time the external connection terminals in the 14 are rewired to be formed and 15, it relates to a wafer level package having an external connection terminal 14. the sealing resin 22 for covering the cultivation line and installed at the same time to expose to the outside. And with the chip terminal 13 from the chip terminals (13A), the re-wiring drawn out position by 15, the circuit region 12, and further drawn out the redistribution traces 15 to be used during a test conducted at the same time as installing the test terminals 16 are connected to, and adapted to expose from a test terminal 16, a sealing resin 22. ; Preliminary tests, final test chip terminals