Scalable, high-performance, global together circuit diagram for a network processor module with more path operation of a multiprocessor - a - chip - system

摘要

The apparatus, which comprises:a plurality of masters, configured in a plurality of clusters;a plurality of targets, wherein each target resource comprises a commonly used, which is accessible to the plurality of masters;an interconnection, which sets a plurality of bus line between the plurality of clusters and the plurality of targets and cross rails are connected together circuits, the bus line sets with a command bus, a pull - data bus for the writing of target data and a push - data bus for the reading out of the target data; anda multiplex circuit for each command bus, pull - data bus and push - data bus, in order to selectively a given cluster to connect with a given target, so that commands and data between the given clusters and the given target are passable.