METHOD AND SYSTEM FOR LOW-POWER LEVEL-SENSITIVE SCAN DESIGN LATCH WITH POWER-GATED LOGIC

摘要

PROBLEM TO BE SOLVED: To provide a method and system for low-power level-sensitive scan design latch with power-gated logic.;SOLUTION: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC) 100 is provided. When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent the electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.;COPYRIGHT: (C)2008,JPO&INPIT